Many devices in computer systems utilize dynamic random access memories (DRAMS). The DRAMS are typically tested each time the system, or a device containing DRAMS, is turned on or "powered up". The tests may be part of a self-evaluation sequence which the system or device performs on various circuits to determine if the circuits are capable of correctly performing specific tasks or series of tasks.
The circuits are typically tested by exercising them, that is, sequencing them through a specific series of operations using predetermined input signal vectors. Signals generated at various internal and/or external nodes of the circuit under test may be monitored throughout the test sequence and, at predetermined points in the sequence, compared with corresponding expected signals. The generated signals and the expected signals will typically match if the circuit is functioning properly.
If a large number of nodes are monitored, the signals may be encoded to produce smaller output, or signature, vectors. The signature vectors can then be compared with similarly encoded expected output signal vectors and the results analyzed to determine if the circuit is functioning properly.
The tests are usually designed such that a circuit is fully exercised, that is, specific operations are performed which utilize the complete range of capabilities of the circuit. To thoroughly test a memory, for example, the memory controller is tested, and each addressable multi-bit memory storage location, as well as the individual bit-storage locations, is tested. The addressable locations are tested to determine if they are properly accessed using the associated addresses, and the bit-storage locations are tested to determine if they are capable of correctly storing both ONES and ZEROS.
The addressable multi-bit memory locations typically store data and associated error correction code (ECC) redundancy bits. Each time data is stored in a memory location the associated ECC bits are also stored therein. Thus, to test a memory location, several read and write operations are required, namely, a write and corresponding read operation to write and then read both a data pattern of ONES and ZEROS and the associated ECC bits; a write and corresponding read operation to write and then read the binary inverse or compliment of both the data pattern and the ECC bits associated with the inverted data; and a series of operations to test each ECC bit location by writing and reading data which will result in each of the ECC bit locations storing both a ONE and a ZERO.
As the memories become larger and larger, sequentially testing each addressable storage location and each bit-storage location takes more and more time. Thus a test which reads and writes the addressable storage locations and tests each bit-storage location, including ECC bit storage locations, in a shorter period of time using fewer write and read operations is desirable.
Testing sequences for DRAMS are typically quite complex and time consuming because of the DRAMS' dynamic refresh operations. Refresh operations are controlled exclusively by the characteristics of the DRAM and are performed at times dictated by an associated timer. Thus the DRAM may already be engaged in any number of system-controlled activities, including testing, when a refresh operation is to be performed. The refresh operation may alter the node signals that make up an output vector. Accordingly, the test output vector may not match the expected output vector, even if the circuit is functioning properly.
Moreover, to completely test the DRAM, the refresh operation should be tested, also. If the DRAM is otherwise functioning properly but has a faulty refresh cycle, stored data may be lost. Thus a test which includes the refresh operation and also provides output vectors unaffected by the refresh operation is desirable.